1. Technical Field of the Invention
The invention relates generally to communication systems; and, more particularly, it relates to decoding of signals within such communication systems.
2. Description of Related Art
Data communication systems have been under continual development for many years. One such type of communication system that has been of significant interest lately is a communication system that employs turbo codes. Another type of communication system that has also received interest is a communication system that employs LDPC (Low Density Parity Check) coded modulation. A primary directive in these areas of development has been to try continually to lower the error floor within a communication system. The ideal goal has been to try to reach Shannon's limit in a communication channel. Shannon's limit may be viewed as being the data rate to be used in a communication channel, having a particular SNR (Signal to Noise Ratio), that achieves error free transmission through the communication channel. In other words, the Shannon limit is the theoretical bound for channel capacity for a given modulation and code rate.
LDPC code has been shown to provide for excellent decoding performance that can approach the Shannon limit in some cases. For example, some LDPC decoders have been shown to come within 0.3 dB (decibels) from the theoretical Shannon limit. While this example was achieved using an irregular LDPC code of a length of one million, it nevertheless demonstrates the very promising application of LDPC codes within communication systems.
Typical decoding of LDPC coded modulation signals is performed based on a bipartite graph of a given LDPC code such that the graph includes bit nodes and check nodes. The I, Q (In-phase, Quadrature) values associated with received symbols are associated with a symbol node, and that symbol node is associated with corresponding bit nodes. Bit metrics are then calculated for the individual bits of the corresponding symbols, and those bit metrics are provided to the bit nodes of the bipartite graph of the given LDPC code. Edge information corresponding to the edges that interconnect the bit nodes and the check nodes is calculated, and appropriately updated, and communicated back and forth between the bit nodes and the check nodes during iterative decoding of the LDPC coded signal. Therefore, such LDPC decoding is typically performed with respect to the bit nodes and the check nodes of the LDPC bipartite graph. One disadvantage of this approach to LDPC decoding is that it can be very memory and processing resource consumptive. Even in instances where there are sufficient memory and processing resources available, the previous approaches to perform LDPC decoding typically do not give a sufficiently high level of performance for some applications. With the ever-improvements developments in memory management and processing resource allocation, a higher performance means by which LDPC coded modulation signals may be decoded would be desirable.